1. Field of the Invention
This invention relates to a CMOS output circuit provided in the output stage of a CMOS semiconductor integrated circuit.
2. Description of the Related Art
With higher packing density and larger-scale integration, semiconductor integrated circuits (ICs) and large-scale integrated circuits (LSIs) operate even faster but consume more power.
In the output circuit built in a high-speed CMOS IC, to shorten the charging and discharging time of the output load capacity, the W/L or the conductance gm of the MOS transistor in the IC is set at a large value so that large current may be drawn from the output terminal. Here, W in the W/L is the gate length, or the gate width, of the MOS transistor, and L is the distance between the source and drain, or the channel length. A minimum channel length that has been achieved to date is nearly 1.5 .mu.m.
To make W/L larger, it is necessary to make L smaller and W larger. With higher integration, however, it is impossible to increase W as desired and a maximum value recently achieved is as small as 2,500 .mu.m.
On the other hand, to reduce the size of a chip into which more and more semiconductor components are being squeezed, a CMOS inverter circuit is usually used in the output circuit.
FIG. 1 shows an equivalent circuit for a conventional output circuit built in a CMOS IC.
The output circuit is an inverter circuit comprising a p-channel MOS transistor 11 and an n-channel MOS transistor 12. The source of the p-channel MOS transistor 11 is connected to the positive power supply Vcc, whereas the source of the n-channel MOS transistor 12 is connected to the negative power supply Vss. The drains of both MOS transistors 11 and 12 are connected to each other, and this common drain is then connected to the output terminal 13.
Similarly, the gates of both MOS transistors 11 and 12 are connected to one another, and this common gate receives the IC internal signal.
The inverter is formed on an IC chip such as a silicon semiconductor, which is housed in a package made of synthetic resin, ceramic, or the like. On the IC chip, a plurality of pads including a power supply pad are formed. The transmission and reception of signals and supply voltages between these pads and external circuitry are performed via the lead frame, boding wires, and others.
In FIG. 1, parasitic inductances and capacitances on the lead frame, bonding wires, and others are indicated by reference characters L1 through L3 and C1 through C3. RL and CL represents the load resistance and capacitance, respectively.
In the inverter circuit, the parasitic components cause overshoot and undershoot in the output waveform. Such overshoot and undershoot increase in proportion to the magnitude of the output current from the inverter circuit, or the W/L of the MOS transistor.
For example, it is assumed that the W/L of the p-channel MOS transistor 11 is 1,690 .mu.m/1.5 .mu.m and that for the n-channel MOS transistor 12 is 704 .mu.m/1.5 .mu.m. It is also assumed that for the lead frame, boding wires, and other, each of the parasitic capacitances C1, C2, and C3 is 10 pF, and each of the parasitic inductances L1, L2, and L3 is 13 nH. Further, it is assumed that the load capacitance CL is 50 pF; the load resistance RL 500 .OMEGA.; the voltage of the positive power supply Vcc+5V; and the voltage of the negative power supply Vss 0V.
Under such conditions, when the signals supplied to the gates of both MOS transistors 11 and 12 were changed, a waveform simulating the resulting changes in the output signal was obtained, as shown in FIG. 2, by the SPICE simulation.
As seen from FIG. 2, an output waveform corresponding to the switching of the input signal has overshoot and undershoot. As a result, the output terminal 13 suffers from ringing whose voltage peak is nearly 4.1V, which is the difference between the 1.6V undershoot and the -2.5V overshoot.
The parasitic components cause overshoot and undershoot in the output waveform because current changes. Recent higher-speed semiconductor devices, however, involves larger changes in current, which increases the effects of parasitic inductance and capacitance to the extend that cannot be neglected.
In a system composed of a plurality of ICs, for example, CMOS ICs, with the positive supply voltage being 5V, the noise margin of each IC normally has a maximum V.sub.IL of 1.5V on the low level side and a minimum V.sub.IH of 3.5V on the high level side. In driving such ICs, if ringing takes place at the output terminal, this will cause the driven ICs to receive the input voltage that exceeds the input noise margin, leading to an increase in drawn current in the driven ICs and faulty operation.